1. Field of the Invention.
The present invention relates to output circuitry having active overvoltage protection. More particularly, the present invention relates to circuitry having an output coupled to a common bus which bus may experience signal potentials exceeding the signal potential associated with the output circuitry. The present invention is an output control circuit having overvoltage protection and means for detecting an overvoltage condition as well as the removal of an overvoltage condition on the common bus and ensuring that the output signal of the output circuitry is maintained through the transition from the overvoltage condition.
2. Description of the Prior Art.
Electrical signal transmission circuits are used to transfer electrical signals of desired amplitude and strength. Signals are transferred from one sub-system to another by way of interfaces, i.e., buses, that couple active devices together. Increasingly, the active devices may not be powered at equivalent potentials. That is, some may be powered by a supply at a nominal level of 5.0 volts, some at a nominal 3.3 volts, and still others at a nominal 2.2 volts.
The systems may be located proximate to one another, or they may be some distance from one another. One example of a proximate system interface requiring one or more bus connections is the coupling of one printed circuit board to another within a computing system, such as through a backplane bus. An example of a remote system interface requiring one or more bus connections is the coupling of one computing system to another, such as through a telephone transmission line that is, effectively, a voice/data bus. More generally, any system used to transfer electrical signals from one point to another, whether digital or analog, requires some arrangement for ensuring that the transfer occurs as smoothly as possible when desired.
As indicated, signal transmission circuits are used to ensure that electrical signals are transferred as accurately and as quickly as possible. Among other means, signal propagation may be established using solid state devices such as semiconductor structures. In particular, metal oxide semiconductor (MOS) active devices are often employed for this purpose. When P-type MOS (PMOS) structures are used in combination with N-type MOS (NMOS) structures in a complementary MOS (CMOS) arrangement, logic HIGH and logic LOW signals may be propagated through the circuit. In a CMOS output circuit, the PMOS transistor, when on, is the pullup transistor that establishes a logic HIGH at the output of the CMOS-based output circuit. When the PMOS transistor is off and the NMOS transistor is on, the NMOS transistor acts as a pulldown transistor that establishes a logic LOW at the output of the CMOS-based output circuit. For CMOS-based logic, for example, a logic HIGH corresponds to a nominal 5.0-volt potential (for a 5.0V power supply) and a nominal 3.3-volt potential (for a 3.3V power supply), while a logic LOW is essentially equivalent to ground (GND) or 0.0-volt.
The potentials associated with HIGH and LOW signals described above are idealized values. In fact, HIGHS and LOWS generally fall within a range of potentials associated with the indicated values. Thus, for a 3.3-volt supply, a HIGH signal may be supplied at 2.6V, for example, while a LOW signal may actually be associated with a 0.7V value. As the potentials of the power supplies used to power circuitry move closer to GND, variations in the potentials applied to those devices take on greater importance. For example, a PMOS transistor powered by a 3.3-volt supply and having an output coupled to a common bus that also has coupled to it an active device powered at 5.0V may experience a significant overvoltage event. That is, the bus may be dominated by a 5.0V nominal potential so that the drain of the PMOS transistor is at a potential substantially higher than the potential of its source and bulk (back gate), which are generally the same. The result is an undesirable current passing from the bus to the power supply of the pullup transistor. Further, a significant overvoltage condition at the pullup transistor""s drain can create an unexpected turning on of that transistor when it is expected to be off. It is therefore of great interest to ensure that the pull up transistor will remain at its selected state during an overvoltage condition at the output of the output circuit.
In order to address this potential problem during an overvoltage condition, overvoltage sense circuits have been developed in order to maintain the pull up transistor in its selected state. In U.S. Pat. No. 5,654,858 issued to Martin et al., a solution for this condition is disclosed. Specifically, Martin apparently establishes a pseudo supply rail that provides to the gate of the pull up transistor a potential matching the greater of the supply potential and the bus potential. In that way, the off state of that transistor is apparently ensured. In an alternative arrangement, Martin creates a blocking sub-circuit that is intended to block an overvoltage signal at the bus from passing back through the pull up transistor.
Unfortunately, the Martin and other overvoltage protection devices generally rely upon the formation and operation of supplemental devices that can slow the signal propagation effort or that otherwise simply consume chip space. A fairly simple solution to the overvoltage problem is to couple a sense inverter between the output node and ground. The sense inverter detects the overvoltage condition and pulls the higher potential associated with that condition away from the drain of the pull up transistor to be protected. In particular, it turns off the pull up transistor to ensure that there is no current conduction from the bus-tied output node to the supply for the pull-up transistor. That is designed to occur when the potential at the bus exceeds a threshold turn-on voltage Vt of the PMOS transistor.
However, while such a sense device achieves the goal of blocking current from the bus to the high-potential supply of the output circuit, during an overvoltage condition, it has a specific undesirable characteristic. As indicated, the sense inverter coupled to the output node of the output circuit will protect during overvoltage conditions. However, when the pull up transistor is required to be on and maintaining a logic HIGH potential VOH associated with its supply potential, the removal of an overvoltage condition from the bus is not detected immediately and the pull up transistor remains in an off (protected) state. Instead, there is a lag during which the sense circuit continues to control the condition of the pull up transistor in an off state. Only when that control is removed is the pull up transistor turned back on in a manner that provides for the propagation of a logic HIGH signal to the bus. Such a delay is undesirable, particularly when a general goal in semiconductor device operation is faster propagation. Further, under such conditions, an out-of-state logic state could be generated, another undesirable event.
Therefore, what is needed is a protection circuit that detects overvoltage conditions affecting current through the pull up transistor and turns off that pull up transistor. What is also needed is such a protection circuit with overvoltage protection that detects when the overvoltage condition has been removed. Further, what is needed is such a protection circuit that detects the removal of the overvoltage condition and minimizes the delay in turning the pull up transistor back on.
It is an object of the present invention to provide a protection circuit that detects overvoltage conditions affecting current through the pull up transistor and turns off that pull up transistor. It is a further object of the present invention to provide a protection circuit with overvoltage protection that detects when the overvoltage condition has been removed. It is also an object of the present invention to provide such a protection circuit that detects the removal of the condition and minimizes the delay in turning the pull up transistor back on.
These and other objects are achieved in the present invention, which is an output circuit protection circuit designed to minimize the impact on the output circuit operation caused by an overvoltage condition. The protection circuit is couplable between the pull-up transistor of the output circuit to be protected and the output node of that circuit, wherein the output node is coupled to a bus. That bus may be coupled to other circuitry having power supplies exceeding the power supply associated with the output circuit to be protected. Logic control coupled to the sense circuit and the pull up transistor and the pull down transistor generates a signal, based on a signal from the sense circuit that acts to turn off the pull up transistor when an overvoltage condition occurs. It does so by driving the gate of that transistor to the higher potential sensed by the sense circuit.
The protection circuit includes a first protection branch and a second protection branch that act together to sense when the potential at the output node exceeds the supply potential of the output circuit plus a Vt. Those protection branches further act together to transmit a turn-off signal to the pull up transistor. When the overvoltage condition declines, the two branches act to turn the pull up transistor back on virtually when the output node potential reaches a potential equivalent to the high-potential supply rail potential minus a Vt.
The first protection branch preferably includes an output that propagates the sense signal output used to control the condition of the gate of the pull up transistor of the output circuit to be protected. The first protection branch includes a component controlled by the bus-tied output signal and is supplied by the high-potential rail of the circuit to be protected. On the other hand, the second protection branch includes a component controlled by that same high-potential rail and is supplied by the potential of the bus-tied output signal. Together, they act like a comparator in that one branch controls the output sense signal for an overvoltage condition and the other when that condition does not exist. When there is no overvoltage condition, the first branch ensures that the sense signal output by the protection circuit does not interfere with the ordinary operation of the pull up transistor. When the output node exceeds the high-potential rail potential plus a threshold drop, the second protection branch becomes operational and controls the output of a logic signal that forces the pull up transistor off.
A potential-drop component of the first protection branch provides a means by which the protection circuit quickly turns the pull up transistor back on when the overvoltage condition ceases. Specifically, the potential-drop component is preferably a resistive device that tracks the change in potential at the output node as that change occurs. As soon as a threshold potential change is reached sufficient to change the state of a MOS transistor, the sense signal that is output by the protection circuit acts to turn the pull up transistor back on. The rate at which that occurs is substantially faster than exists with current overvoltage protection devices.
The overvoltage protection circuit of the present invention includes a pair of protection branches that generate a signal to turn off a pull up transistor of a circuit to be protected when an overvoltage detection occurs. They also act to turn the pull up transistor back on when that overvoltage condition is released. These and other advantages of the present invention will become apparent upon review of the detailed description, the accompanying drawings, and the appended claims.